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DATA SHEET
SAA7133HL PCI audio and video broadcast decoder
Product specification 2003 Feb 04
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 3 4 5 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 FEATURES General TV video decoder and video scaling TV sound decoder and TV audio I/O PCI and DMA bus mastering Peripheral interface GENERAL DESCRIPTION Introduction Related documents QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING Pins sorted by number Pins grouped by function Pin type FUNCTIONAL DESCRIPTION Overview of internal functions Application examples Software support PCI interface Analog TV standards Video processing TV sound DTV/DVB channel decoding and MPEG TS or PS capture Control of peripheral devices 14 15 16 17 8 8.1 8.2 9 10 11 12 13 13.1 13.2 13.3 13.4 13.5
SAA7133HL
BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
1 1.1 FEATURES General
SAA7133HL
* Package: LQFP128 * Power supply: 3.3 V only * Power consumption of typical application: 1.35 W * PCI-bus Power Management Interface Specification, rev. 1.1, compliant (supported states: D0, D1, D2 and D3-hot) * Power-down state (D3-hot): <20 mW * All interface signals 5 V tolerant * Reference designs available * Software Development Kit (SDK) for Windows (95, 98, NT, 2000 and XP), Video for Windows (VfW), Windows Driver Model (WDM) and Broadcast Driver Architecture (BDA). 1.2 TV video decoder and video scaling * Volume, balance, bass and treble control * Automatic Volume Levelling (AVL) * Incredible Mono, Incredible Stereo * Audio sampling clock can be locked to video frame rate (no drift of audio stream against video stream) * Four analog audio baseband inputs (two stereo pairs) and on-chip stereo ADCs * Supported audio sampling rates: 32, 44.1 and 48 kHz * Input of external audio reference clock, e.g. 24.576 MHz * Output of audio master clock (768 x fs, 512 x fs, 384 x fs or 256 x fs selectable). 1.4 PCI and DMA bus mastering
* All-standards TV decoder: NTSC, PAL and SECAM * Five analog video inputs: CVBS and S-video * Video digitizing by two 9-bit ADCs at 27 MHz * Sampling according ITU-R BT.601 with 720 pixels/line * Adaptive comb filter for NTSC and PAL, also operating for non-standard signals * Automatic TV standard detection * Three level Macrovision copy protection detection according to Macrovision detect specification Rev.1 * Control of brightness, contrast, saturation and hue * Versatile filter bandwidth selection * Horizontal and vertical downscaling or zoom * Adaptive anti-alias filtering * Capture of raw VBI samples * Two alternating settings for active video scaling, e.g. for independent capturing and preview definition * Output in YUV or RGB * Gamma compensation, black stretching. 1.3 TV sound decoder and TV audio I/O
* PCI 2.2 compliant including full Advanced Configuration and Power Interface (ACPI) * 3.3 and 5 V compliant * System vendor ID, etc. via I2C-bus EEPROM * DMA bus master write for video, audio, VBI and TS or PS * Configurable PCI FIFOs, graceful overflow recovery * Packed and planar video formats, overlay clipping * Hardware support for virtual addressing by Memory Management Unit (MMU). 1.5 * Peripheral interface
I2C-bus
master interface: 3.3 and 5 V compatible, 100 and 400 kHz mode
* The device can operate without PCI-bus (using I2C-bus) for stand-alone applications, application note available * Digital video output: ITU, VIP, VMI and ZV formats * Two digital audio outputs: I2S-bus for up to 4 channels * Analog stereo audio output * Integrated analog audio pass-through * Support for analog audio loop back cable to sound card * TS input: serial or parallel * MPEG elementary or program stream input, parallel * General purpose I/O, e.g. for strapping and interrupt * Propagate reset and ACPI state D3.
* BTSC and EIAJ TV sound decoder * dbx-TV Noise Reduction decoding for BTSC systems * FM radio stereo decoding * Input of analog SIF signal and 8-bit ADC at 24.576 MHz * Automatic sound standard detection * Automatic dematrixing (stereo, dual) 2003 Feb 04 3
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
2 2.1 GENERAL DESCRIPTION Introduction
SAA7133HL
The PCI audio and video broadcast decoder SAA7133HL is a highly integrated, low cost and solid foundation for TV capture in the PC, for analog TV and digital video broadcast (DTV and DVB). The various multimedia data types are transported over the PCI-bus by bus-master-write, to optimum exploit the streaming capabilities of a modern host based system (see Fig.1). Legacy requirements are also taken care of. The SAA7133HL meets the requirements of PC Design Guides 98/99 and 2001 and is PCI 2.2 and Advanced Configuration and Power Interface (ACPI) compliant. The analog video is sampled by 9-bit ADCs, decoded by a multi-line adaptive comb filter and scaled horizontally, vertically and by field rate. Multiple video output formats (YUV and RGB) are available, including packed and planar, gamma-compensated or black-stretched.
Analog TV sound is digitized and stereo decoded (BTSC and EIAJ). Audio is streamed digitally via the PCI-bus or the I2S-bus or routed as an analog signal via the loop back cable to the sound card. The SAA7133HL provides a versatile peripheral interface to support system extensions, e.g. MPEG encoding for time shift viewing. The channel decoder for digital video broadcast reception (ATSC or DVB) can re-use the integrated video ADCs. The Transport Stream (TS) or Program Stream (PS) is collected by a tailored interface and pumped through the PCI-bus to the system memory in well-defined buffer structures. Various internal events, or peripheral status information, can be enabled as an interrupt on the PCI-bus.
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I 2C-bus TV TUNER: CABLE TERRESTRIAL SATELLITE IF-PLL: DVB ATV DTV DVB DIGITAL CHANNEL DECODER: VSB QAM OFDM (1)
I 2C-BUS EEPROM
(1)
SIF
CVBS
TS PS
ENCODER: MPEG2
I 2S-bus CVBS S-video audio I/O DECODER FOR TV SOUND AND TV VIDEO WITH TS AND PS INTERFACE AND DMA MASTER INTO PCI-BUS
ITU656
SAA7133HL
PCI-bus
MBL702
(1) Alternatively.
Fig.1
Application diagram for capturing live TV video and audio streams in the PC, with optional extensions for DTV and DVB capture and MPEG encoding for time shift viewing.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
2.2 Related documents
SAA7133HL
This document describes the functionality and characteristics of the SAA7133HL. Other documents related to the SAA7133HL are: * User manual SAA7133HL, describing the programmability * Application note SAA7133HL, pointing out recommendations for system implementation 3 QUICK REFERENCE DATA SYMBOL VDD Ptot Pstandby Tamb 4 PARAMETER supply voltage total power dissipation standby power dissipation ambient temperature
* Data sheets of other devices referred to in this document, e.g: - Tuners: FI1236 for NTSC (US) FI1286 for NTSC (Japan) combi-tuner derivatives for FM radio: FM12x6 - SAA6752HS: MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer.
CONDITIONS
MIN. 3.0 -
TYP. 3.3 1.35 - -
MAX. 3.6 1.6 0.02 70
UNIT V W W C
D3-hot of ACPI
- 0
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP128 DESCRIPTION plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm VERSION SOT425-1
SAA7133HL
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left 1 right 1 sound audio inputs left 2 right 2 analog audio pass-through ANALOG NF/AUDIO INTERFACE 16-BIT STEREO ADC BTSC EIAJ FM DECODER AM DECODER AUDIO OUTPUT MUX I 2S-BUS audio stereo output I 2S-bus AUDIO FEATURE PROCESSING STEREO DAC SIF ANALOG SIF/AUDIO INTERFACE 8-BIT SIF ADC VIDEO PORT FORMAT ITU656
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Philips Semiconductors
PCI audio and video broadcast decoder
BLOCK DIAGRAM
SAA7133HL
PCI INTERFACE CV0 CV1 CVBS S-video inputs ANALOG VIDEO INTERFACE 9-BIT VIDEO ADC
FIFO
CV2 CV3 CV4 TS/PS data TS data
VIDEO SCALER
MATRIX GAMMA
CLIPPING FORMAT
DMA
Fig.2 Block diagram.
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6
digital data inputs
ANALOG VIDEO INTERFACE
9-BIT VIDEO ADC
DIGITAL VIDEO COMB FILTER DECODER SYNCHRONIZATION
PCI-bus
TS/PS PARALLEL OR TS SERIAL STATIC I/O IRQ
FORMAT
GPIO interrupt
PROGRAM REGISTERS
MBL703
I 2C-bus
SAA7133HL
Product specification
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6 PINNING AD[16] C/BE[2]# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE[1]# AD[15] AD[14] AD[13] AD[12] VDDD VSSD PCI_CLK SYMBOL VDDD GNT# REQ# AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] C/BE[3]# IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] VDDD VSSD AD[18] AD[17] 2003 Feb 04 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 AD[11] AD[10] AD[09] AD[08] C/BE[0]# AD[07] AD[06] AD[05] AD[04] AD[03] AD[02] AD[01] AD[00] VDDD VSSD GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 XTALI XTALO
SAA7133HL
SYMBOL
PIN 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
In Section 6.1 all the pins are sorted by number, table 1. The pin description for the functional groups is given in Section 6.2: * Power supply pins, table 2 * Joint Test Action Group (JTAG) test interface pins for boundary scan test, table 3 * I2C-bus multi-master interface, table 4 * PCI interface pins, table 5 * General purpose interface (pins GPIO) and the main functions, table 6 * Analog interface pins, table 7. The characteristics of the pin types are detailed in Section 6.3, table 8. The SAA7133HL is packaged in a rectangular LQFP (low profile quad flat package) with 128 pins (see Fig.3). 6.1 Pins sorted by number Pins sorted by number
Table 1
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL VSSD VDDD V_CLK GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 VDDD VSSD GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO27 GPIO26 GPIO25 SCL SDA VDDD VSSD LEFT2 VDDA LEFT1 VSSA RIGHT1 VREF0 RIGHT2 VREF1 VREF2 OUT_RIGHT OUT_LEFT 2003 Feb 04
PIN 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 8 SIF VREF3 VSSA CV2_C VDDA VREF4
SYMBOL PROP_RST
PIN 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
DRCV_Y VSSA CV0_Y VDDA CV1_Y DRCV_C CV3_C VSSA CV4 TRST TCK TMS TDO TDI INT_A PCI_RST# VSSD
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6.2 Pins grouped by function Power supply pins PIN 97, 108, 113 and 119 95, 110 and 115 20, 39, 55, 64, 74, 93 and 128 TYPE AG AS VG DESCRIPTION analog ground for integrated analog signal processing
SAA7133HL
Table 2
SYMBOL VSSA VDDA VSSD
analog supply voltage for integrated analog signal processing digital ground for digital circuit, core and I/Os
VDDD
1, 19, 38, 54, VS 65, 73 and 92 JTAG test interface pins PIN 121 122 123 124 125 I I I O I TYPE
digital supply voltage for digital circuit, core and I/Os. The next generation products of this product family will be pin compatible to its predecessors but with a core supply voltage of 1.8 V.
Table 3
SYMBOL TRST TCK TMS TDO TDI Table 4
DESCRIPTION test reset input: drive LOW for normal operating (active LOW) test clock input: drive LOW for normal operating test mode select input: tie HIGH or let float for normal operating test serial data output: 3-state test serial data input: tie HIGH or let float for normal operating
I2C-bus multi-master interface PIN 90 91 105 TYPE IO2 IO2 GO DESCRIPTION serial clock input (slave mode) or output (multi-master mode) serial data input and output; always available propagate reset and D3-hot output; to peripheral board circuitry (active LOW)
SYMBOL SCL SDA PROP_RST
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 5
SAA7133HL
PCI interface pins, PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements PIN 40 127 4 to 11, 14 to 18, 21 to 23, 34 to 37, 41 to 44 and 46 to 53 12, 24, 33 and 45 32 25 27 26 29 13 28 3 2 126 30 31 TYPE PI PI DESCRIPTION PCI clock input: reference for all bus transactions, up to 33.33 MHz PCI reset input: will 3-state all PCI pins (active LOW)
SYMBOL PCI_CLK PCI_RST# AD[31] to AD[00]
PIO and multiplexed address and data input or output: bi-directional, 3-state T/S
C/BE[3]# to C/BE[0]# PAR FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# REQ# GNT# INT_A PERR# SERR#
PIO and command code input or output: indicates type of requested transaction and T/S byte enable, for byte aligned transactions (active LOW) PIO and parity input or output: driven by the data source, even parity over all pins AD T/S and C/BE# PIO and frame input or output: driven by the current bus master (owner), to indicate S/T/S the beginning and duration of a bus transaction (active LOW) PIO and target ready input or output: driven by the addressed target, to indicate S/T/S readiness for requested transaction (active LOW) PIO and initiator ready input or output: driven by the initiator, to indicate readiness to S/T/S continue transaction (active LOW) PIO and stop input or output: target is requesting the master to stop the current S/T/S transaction (active LOW) PI initialization device select input: this input is used to select the SAA7133HL during configuration read and write transactions
PIO and device select input or output: driven by the target device, to acknowledge S/T/S address decoding (active LOW) PO PI PO and O/D PCI request output: the SAA7133HL requests master access to PCI-bus (active LOW) PCI grant input: the SAA7133HL is granted to master access PCI-bus (active LOW) interrupt A output: this pin is an open-drain interrupt output, conditions assigned by the interrupt register
PIO and parity error input or output: the receiving device detects data parity error S/T/S (active LOW) PO and O/D system error output: reports address parity error (active LOW)
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 6 GPIO pins and functions; note 1 FUNCTION SYMBOL GPIO27 GPIO26 GPIO25 V_CLK GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 PIN 87 88 89 66 56 57 58 59 60 61 67 TYPE GIO GIO GIO GO GIO GIO GIO GIO GIO GIO GIO AUDIO AND VIDEO PORT OUTPUTS A_SDO (I2S-bus 1 data) A_WS (I2S-bus word select) A_SCK (I2S-bus clock) V_CLK (also gated) HSYNC VSYNC - - - VAUX2; A_CLK_master, A_REF_CLK VAUX1 (e.g. VACTIVE); A_SDO_aux, I2S-bus 2 data - VP[7:0] for formats: ITU-R BT.656, VMI, VIP (1.1, 2.0), etc. VP extension for 16-bit formats: ZV, VIP-2, DMSD, etc. TS AND PS CAPTURE INPUTS - - - - - TS_LOCK (channel decoder locked) TS_S_D (bit-serial data) TS_CLK (<33 MHz) TS_SOP (packet start) - -
SAA7133HL
RAW DTV/DVB OUTPUTS - - - ADC_CLK (out) - - - - X_CLK_IN
GPIO R/W R/W R/W - R/W, INT R/W R/W R/W R/W, INT
ADC_C[0] (LSB) R/W, INT
ADC_Y[0] (LSB) R/W
GPIO16 GPIO15 to GPIO8 GPIO7 to GPIO0
68
GIO
TS_VAL (valid flag) -
- ADC_Y[8:1]
R/W, INT R/W
69 to 72 GIO and 75 to 78 79 to 86 GIO
TS_P_D[7:0] (transport ADC_C[8:1] stream or program stream, byte-parallel data)
R/W
Note 1. The SAA7133HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions can be selected: a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video, with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes. b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by Start Of Packet (SOP); in byte-parallel or bit-serial protocol. c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB channel decoder. d) Program Stream (PS) capture input, e.g. from an external MPEG encoder chip. e) GPIO: as default (no other function selected); static (no clock); read and write from or to individually selectable pins; latching `strap' information at system reset time. f) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A).
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 7
SAA7133HL
Analog interface pins, the SAA7133HL offers an interface for analog video and audio signals. The related analog supply pins are included in this table PIN 62 63 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 TYPE CI CO AI AS AI AG AI AR AI AR AR AO AO AO AI AR AG AI AS AR AR AG AI AS AI AR AI AG AI quartz oscillator output analog audio stereo left 2 input or mono input analog supply voltage (3.3 V) analog audio stereo left 1 input or mono input; default analog pass-through to pin OUT_LEFT after reset analog ground (for audio) analog audio stereo right 1 input or mono input; default analog pass-through to pin OUT_RIGHT after reset analog reference ground for audio Sigma Delta ADC; to be connected VSSA analog audio stereo right 2 input or mono input analog reference voltage for audio Sigma Delta ADC; to be connected to VDDA and via a 220 nF capacitor to pin VREF0 analog reference voltage for audio Sigma Delta ADC; to be supported with two parallel capacitors of 47 and 0.1 F to VSSA analog audio stereo right channel output; 1 V (RMS) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 F analog audio stereo left channel output; 1 V (RMS) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 F analog output for test and debug purpose sound IF input from TV tuner (4.5 to 9.2 MHz); coupling capacitor of 47 pF after the termination with 50 analog reference voltage for audio FIR-DAC and SCART audio input buffer; to be supported with two parallel capacitors of 47 and 0.1 F to VSSA analog ground composite video input (mode 2) or C input (modes 6 and 8) analog power supply (3.3 V) analog reference voltage; to be supported with a capacitor of 220 nF VSSA differential reference connection (for CV0 and CV1); to be supported with a capacitor of 47 nF to VSSA analog ground composite video input (mode 0) or Y input (modes 6 and 8) analog supply voltage (3.3 V) composite video input (mode 1) or Y input (modes 7 and 9) differential reference connection (for CV2, CV3 and CV4); to be supported with a capacitor of 47 nF to VSSA composite video input (mode 3) or C input (modes 7 and 9) analog ground composite video input (mode 4) DESCRIPTION quartz oscillator input: 32.11 or 24.576 MHz
SYMBOL XTALI XTALO LEFT2 VDDA LEFT1 VSSA RIGHT1 VREF0 RIGHT2 VREF1 VREF2 OUT_RIGHT OUT_LEFT PROP_RST SIF VREF3 VSSA CV2_C VDDA VREF4 DRCV_Y VSSA CV0_Y VDDA CV1_Y DRCV_C CV3_C VSSA CV4
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6.3 Pin type Characteristics of pin types and remarks DESCRIPTION analog ground analog input; video, audio and sound analog output analog reference support pin analog supply voltage (3.3 V) CMOS input; 3.3 V signal level (not 5 V tolerant) CMOS output; 3.3 V signal level (not 5 V tolerant) digital input (GPIO); 3.3 V signal level (5 V tolerant) digital input/output (GPIO); 3.3 V signal level (5 V tolerant) digital output (GPIO); 3.3 V signal level (5 V tolerant) JTAG test input
SAA7133HL
Table 8
PIN TYPE AG AI AO AR AS CI CO GI GIO GO I IO2 O O/D PI PIO PO S/T/S T/S VG VS With overscore or #
digital input and output of the I2C-bus interface; 3.3 and 5 V compatible, auto-adapting JTAG test output open-drain output (for certain PCI pins); multiple clients can drive LOW at the same time, wired-OR, floating back to 3-state over several clock cycles input according to PCI requirements input and output according to PCI requirements output according to PCI requirements sustained 3-state (for certain PCI pins); previous owner drives HIGH for one clock cycle before leaving to 3-state 3-state I/O according to PCI requirements; bi-directional ground for digital supply supply voltage (3.3 V) this pin or `signal' is active LOW, i.e. the function is `true' if the logic level is LOW
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
105 PROP_RST
104 OUT_LEFT
128 VSSD 127 PCI_RST#
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103 OUT_RIGHT 102 VREF2 101 VREF1 100 RIGHT2 99 VREF0 98 RIGHT1 97 VSSA 96 LEFT1 95 VDDA 94 LEFT2 93 VSSD 92 VDDD 91 SDA 90 SCL 89 GPIO25 88 GPIO26 87 GPIO27 86 GPIO0 85 GPIO1 84 GPIO2 83 GPIO3 82 GPIO4 81 GPIO5 80 GPIO6 79 GPIO7 78 GPIO8 77 GPIO9 76 GPIO10 75 GPIO11 74 VSSD 73 VDDD 72 GPIO12 71 GPIO13 70 GPIO14 69 GPIO15 68 GPIO16 67 GPIO17 66 V_CLK 65 VDDD VSSD 64
117 DRCV_C
113 VSSA 112 DRCV_Y
111 VREF4 110 VDDA
108 VSSA 107 VREF3 GPIO20 59 GPIO19 60
119 VSSA 118 CV3_C
109 CV2_C
116 CV1_Y
115 VDDA 114 CV0_Y
126 INT_A
121 TRST
123 TMS
124 TDO
122 TCK
120 CV4
125 TDI
VDDD GNT# REQ# AD[31] AD[30] AD[29] AD[28] AD[27] AD[26]
1 2 3 4 5 6 7 8 9
AD[25] 10 AD[24] 11 C/BE[3]# 12 IDSEL 13 AD[23] 14 AD[22] 15 AD[21] 16 AD[20] 17 AD[19] 18 VDDD 19 VSSD 20 AD[18] 21 AD[17] 22 AD[16] 23 C/BE[2]# 24 FRAME# 25 IRDY# 26 TRDY# 27 DEVSEL# 28 STOP# 29 PERR# 30 SERR# 31 PAR 32 C/BE[1]# 33 AD[15] 34 AD[14] 35 AD[13] 36 AD[12] 37 VDDD 38 VSSD 39 PCI_CLK 40 AD[11] 41 AD[10] 42 AD[09] 43 AD[08] 44 C/BE[0]# 45 AD[07] 46 AD[06] 47 AD[05] 48 AD[04] 49 AD[03] 50 AD[02] 51 AD[01] 52 AD[00] 53 VDDD 54 VSSD 55 GPIO23 56 GPIO22 57 GPIO21 58 GPIO18 61 XTALI 62 XTALO 63
SAA7133HL
106 SIF
MBL704
Fig.3 Pin configuration.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7 7.1 FUNCTIONAL DESCRIPTION Overview of internal functions
SAA7133HL
The SAA7133HL is able to capture TV signals over the PCI-bus in personal computers by a single chip (see Fig.4).
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5 analog video inputs digital video output
GPIO transport stream or program stream reset input digital audio output
I 2C-bus
stereo output
stereo stereo input 1 input 2
IF sound input
INPUT SELECTION CLAMP AND GAIN CONTROL 9-BIT ADC 9-BIT ADC
VIDEO PORT (DIGITAL)
I 2C-BUS INTERFACE
PARALLEL OR SERIAL INTERFACE
I 2S-BUS OUTPUT
ANALOG AUDIO I/O PASS-THROUGH (DEFAULT)
SIF ADC
DECODER (NTSC, PAL, SECAM) LLC ADAPTIVE COMB FILTER
AUDIO 16-BIT DAC PROPAGATE RESET
AUDIO 16-BIT DAC
AUDIO 16-BIT ADC
AUDIO 16-BIT ADC
SIF DEMOD
FLC
VIDEO SCALER MATRIX 3-D GAMMA RAW VBI FORMAT PROGRAM PROGRAM SET SET VIDEO FIFOS DMA CONTROL AUDIO FIFOS DMA CONTROL
AUDIO FEATURE PROCESSING: INCREDIBLE MONO OR STEREO
BTSC EIAJ
SAA7133HL
BOUNDARY SCAN TEST
OSCILLATOR
PCI-BUS INTERFACE
ACPI POWER MANAGEMENT
MBL705
PCI-bus
test
x-tal
Fig.4 Functional block diagram.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
The SAA7133HL incorporates two 9-bit video ADCs and the entire decoding circuitry of any analog TV signal: NTSC, PAL and SECAM, including non-standard signals, such as playback from a VCR. The adaptive multi-line comb filter provides superb picture quality, component separation, sharpness and high bandwidth. The video stream can be cropped and scaled to the needs of the application. Scaling down as well as zooming up is supported in the horizontal and vertical direction, and an adaptive filter algorithm prevents aliasing artifacts. With the acquisition unit of the scaler two different `tasks' can be defined, e.g. to capture video to the CPU for compression, and write video to the screen from the same video source but with different resolution, colour format and frame rate. The SAA7133HL contains TV sound stereo decoding from Sound IF (SIF), for the BTSC and EIAJ stereo sound standards, FM and AM mono sound and also non-standard signals. Baseband stereo audio sampling is also implemented, e.g. for capturing from a camcorder or other external devices. The audio sampling rate can be locked to the video frame rate to ensure synchronization (lip-sync) between the video and audio data flow, e.g. for storage, compression or time shift viewing applications. The SAA7133HL incorporates analog audio pass-through and support for the analog audio loop back cable to the sound card function. The decoded video streams are fed to the PCI-bus, and are also applied to a peripheral streaming interface, in ITU, VIP or VMI format. A possible application extension is on-board hardware MPEG compression, or other feature processing. The compressed data as PS or TS is fed back through the peripheral interface, in parallel or serial format, to be captured by the system memory through the PCI-bus. The Transport Stream (TS) from a DTV/DVB channel decoder can be captured through the peripheral interface in the same way. Audio, video and transport streams are collected in a configurable FIFO with a total capacity of 1 kbyte. The DMA controller monitors the FIFO filling degree and master-writes the audio and video stream to the associated DMA channel. The virtual memory address space (from OS) is translated into physical (bus) addresses by the on-chip hardware Memory Management Unit (MMU). The application of the SAA7133HL is supported by reference designs and a set of drivers for the Windows operating system (Video for Windows and Windows Driver Model compliant). 7.2 Application examples
SAA7133HL
The SAA7133HL enables PC TV capture applications both on the PC mother board and on PCI add-on TV capture cards. Figures 5 and 6 illustrate some examples of add-on card applications. Figure 5 shows the basic application to capture video from analog TV sources. The proposed tuner types incorporate the RF tuning function and the IF downconversion. Usually the IF downconversion stage also includes a single channel and analog sound FM demodulator. The Philips tuners FI1286 (Japan) and FI1236MK2 (USA and other NTSC countries) are suitable for M standard. The FM12x6 are special versions for additional FM radio reception. All types are suited for terrestrial broadcast and for cable reception. The tuners provide composite video CVBS and audio as second SIF. These analog video and sound signals are fed to the appropriate input pins of the SAA7133HL. Further analog video input signals, CVBS and/or Y-C, can be connected via the board back-panel, or the separate front connectors, e.g. from a camcorder. Accompanying stereo audio signals can also be fed to the SAA7133HL. Video is digitized and decoded to YUV. TV sound is digitized and decoded. The SAA7133HL is able to decode stereo audio according to BTSC [also including the Second Audio Program (SAP)] and stereo/dual audio according to EIAJ. In addition mono decoding of FM and AM sound is possible. The digital streams are pumped via DMA into the PCI memory space. The SAA7133HL incorporates means for legacy analog audio signal routing. The on-chip audio DACs convert the digital decoded stereo signal into analog audio. This analog audio input signal is fed via an analog audio loop back cable into the line-in of a legacy sound card. An external audio signal, that would have otherwise connected directly to the sound card, is now routed through the SAA7133HL. This analog pass-through is enabled as default by a system reset, i.e. without any driver involvement and before system set-up. During the power-up procedure, the SAA7133HL will investigate the on-board EEPROM to load the board specific system vendor ID and board version ID into the related places of the PCI configuration space. The board vendor can store other board specific data in the EEPROM that is accessible via the I2C-bus.
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Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth handbook, full pagewidth
TV CAPTURE PCI CARD TV cable or terrestrial TV TUNER AND IF-PLL I 2C-bus CVBS SIF analog audio loop back cable
CVBS S-video audio line-in DMA MASTER INTO PCI DECODER FOR TV SOUND AND TV VIDEO
SOUND CARD
I 2C-BUS EEPROM SYSTEM VENDOR ID
SAA7133HL
PCI-bus: digital video, digital audio, raw VBI, TS, PS
SOUTH BRIDGE ISA SYSTEM MEMORY
NORTH BRIDGE
AGP
VGA AND LOCAL MEMORY
FSB
CPU AND CACHE MEMORY
MBL708
Fig.5 Basic TV capture with BTSC and EIAJ stereo decoding.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Figure 6 shows an application extension with VSB channel decoding for DTV-ATSC or peripheral MPEG encoding. A combi-tuner, e.g. Philips NTSC tuner FM1236, provides a dedicated DTV-IF signal that can be routed directly to the channel decoder device, which converts also the decoded signal into a DTV (or BS-digital) Transport Stream (TS). The SAA7133HL captures this TS via the dedicated peripheral interface into the configurable internal FIFO for DMA into the PCI memory space.
SAA7133HL
The packet structure is maintained in a well-defined buffer structure in the system memory, and therefore can easily be sorted (de-multiplexed) by the CPU for proper MPEG decoding. Alternatively, an external MPEG encoder chip can be inserted into the data path. This device gets the video data in ITU-R BT.656 format and the audio data in I2S format from the SAA7133HL and gives back the MPEG encoded program stream to the SAA7133HL.
handbook, full pagewidth
HYBRID TV CAPTURE PCI CARD IF TV TUNER IF DIGITAL IF-PLL DTV-VSB CHANNEL DECODER (1)
analog TV cable or terrestrial and DTV-ATSC terrestrial
I 2C-bus
ANALOG IF-PLL CVBS SIF TS PS ITU DECODER FOR TV SOUND AND TV VIDEO I2S MPEG AV (1) ENCODER SOUND CARD
CVBS S-video audio line-in DMA MASTER INTO PCI
analog audio loop back cable I 2C-BUS EEPROM SYSTEM VENDOR ID
SAA7133HL
PCI-bus: digital video, digital audio, raw VBI, TS, PS
SOUTH BRIDGE ISA SYSTEM MEMORY
NORTH BRIDGE
AGP
VGA AND LOCAL MEMORY
FSB
CPU AND CACHE MEMORY
MBL707
(1) Alternatively.
Fig.6 Hybrid TV capture board with MPEG encoding or DTV channel decoder, e.g. VSB-ATSC.
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Product specification
PCI audio and video broadcast decoder
7.3 7.3.1 Software support DEVICE DRIVER
SAA7133HL
All platform related drivers support the following: * Video preview and capture interfaces * Audio control and audio capture interfaces * Custom application interface, that enables the development of specialized applications in cases where the published direct show Application Programmers Interface (API) may not be sufficient.
A complex and powerful software packet is provided for all PCI chips from the SAA713x family. This packet includes plug-and-play driver and capture driver installations for all commonly used 32-bit Windows platforms.
Table 9
Microsoft Operation System (MS-OS) support DRIVER SUPPORT Device access is contained within a VxD. The Video for Windows (VfW) capture driver interface is a 16-bit user-mode interface. Device access is contained in a kernel-mode driver. The VfW capture driver interface is a 32-bit user-mode interface.
MS-OS Windows 95 Windows NT4
Windows 98 and Device access is contained in a kernel streaming Windows Driver Model (WDM) driver. The Windows ME capture driver interface is based on Microsoft `direct show' technology. Windows 2000 Windows XP The driver is binary-compatible with the Windows 98/ME driver and validated for passing the Microsoft WHQL test for getting the Win2000 driver signature. The driver is binary-compatible with the Windows 98/ME driver and validated for passing the Microsoft WHQL test for getting the WinXP driver signature. VBI, together with a crossbar for input source selection and a TV audio filter for controlling the TV sound standards. The TV tuner filter is a separate child driver and supports the control of all common Philips MK2 and MK3 tuners. The typical filter structure is shown in Fig.7.
7.3.2
SUPPORTING WDM
The WDM driver is implemented as a stream class mini-driver and provides a Kernel Streaming (KS) filter with output pins for audio, video preview, video capture and
handbook, full pagewidth
IAMTVTuner Country / standard TV / FM Radio Channelselect Autoscan Antenna / cable
IAMTVAudio Mono / stereo Dual language SAP
IAMCrossbar Video input channel Audio input channel Link related stream
IAMAnalogVideoDecoder Timing constant Video standard Signal lock status IAMVideoProcAmp Brightness, contrast, saturation Hue, sharpness IAudio7134 Enable loopback video preview
TV AUDIO TV TUNER external audio input CVBS input S-Video input CROSSBAR SAA713x CAPTURE DRIVER
video capture VBI capture audio capture
MBL700
Fig.7 WDM capture driver filters.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.3.3 SOFTWARE DEVELOPMENT KIT FOR CUSTOMER
RELATED APPLICATIONS
SAA7133HL
COM based class library supports interfaces for c++ as well as for Visual Basic and provides methods to: * Select one SAA713x device (in case that more than one device is plugged into the PC) * Capture video into a fixed buffer (including clipping) * Capture audio (baseband stereo input or decoded TV sound) over the PCI-bus into the memory (for PC-VCR application) * Capture video to a stream of buffers over VBI * Capture transport streams (MPEG data) from a channel decoder chip (OFDM, VSB, QAM) for supporting digital TV applications, or from an on-board MPEG encoder chip that is fed by the video output port of the SAA713x * Capture raw VBI sample stream to a stream of buffers over the PCI-bus * Access to the I2C-bus master and GPIO for controlling other peripheral circuits.
The SAA7133HL device is controlled by a LOW-level Hardware Abstraction Layer (HAL), contained within a device driver. This platform-independent HAL initializes and controls the device and responds to interrupts forwarded by a device driver. The HAL consists of objects representing the major device components (video and audio decoder, GPIO pins, I2C-bus master) and also provides classes that can be created to represent buffers and active streams. The driver provides operating system services and forwards interrupts to the HAL. A set of proxy services extends the HAL interface out into user-mode. This is exposed to applications in the form of a COM interface, 34COM.dll. Figure 8 shows these layers of software. In addition to the capture driver, this API provides the whole range of functionality to control the device. This
handbook, full pagewidth
SAA7130
SAA7133
SAA7134
SAA7135
hardware layer
3xHAL WDM TUNER DRIVER
hardware abstraction layer integrated in OS device driver
WDM-CAPTURE DRIVER
MS-Windows system layer
34API.dll
driver access via Microsoft "DirectShow"
MS-Windows layer for "dynamic link libraries" MS-Windows application layer
MBL701
34URD.dll
34COM.dll
URD312.exe
.exe
Fig.8 Software layer structure.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
The API adapts to the different kernel-mode implementations, so that one common 34COM can be used on all Windows operating systems in the same way (see Fig.9). The SDK for the SAA7133HL contains the detailed description of the important software components such as API documentation for streaming, I2C-bus and GPIO access. The provided sample code will introduce the user into working with this interface. All necessary header and library files are provided. 7.4 7.4.1 PCI interface
SAA7133HL
PCI CONFIGURATION REGISTERS
The PCI interface of the SAA7133HL complies with the "PCI specification 2.2" and supports power management and Advanced Configuration and Power Interface (ACPI) as required by the "PC Design Guide 2001". The PCI specification defines a structure of the PCI configuration space that is investigated during the boot-up of the system. The configuration registers (see Table 10) hold information essential for plug-and-play, to allow system enumeration and basic device set-up without depending on the device driver, and support association of the proper software driver. Some of the configuration information is hard-wired in the device; some information is loaded during the system start-up. The device vendor ID is hard coded to 11 31H, which is the code for Philips as registered with PCI-SIG. The device ID is hard coded to 71 33H.
handbook, halfpage
3xHAL NT4.0
3xHAL WDM
3xHAL VxD
34API.dll
34COM.dll
MBL699
Fig.9 Adaptation to different kernels.
During power-up, initiated by PCI reset, the SAA7133HL fetches additional system information via the I2C-bus from the on-board EEPROM, to load actual board type specific codes for the system vendor ID, sub-system ID (board version) and ACPI related parameters into the configuration registers.
Table 10 PCI configuration space registers FUNCTION Device vendor ID Device ID Revision ID Class code Memory address space required System (board) vendor ID Sub-system (board version) ID Note 1. X = don't care. REGISTER ADDRESS (HEX) 00 and 01 02 and 03 08 09 to 0B 10 to 13 2C and 2D 2E and 2F VALUE (HEX) 11 31 71 33 F0 04 80 00 XXXXXXXX XXXXXXXX XXXXX000 00000000 (b) loaded from EEPROM loaded from EEPROM REMARK for Philips for SAA7133HL or higher multimedia 2 kbytes; note 1
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.4.2 ACPI AND POWER STATES
SAA7133HL
The "PCI specification 2.2" requires support of "Advanced Configuration and Power Interface specification 1.0" (ACPI); more details are defined in the "PCI Power Management Specification 1.0". The power management capabilities and power states are reported in the extended configuration space. The main purpose of ACPI and PCI power management is to tailor the power consumption of the device to the actual needs. The SAA7133HL supports all four ACPI device power states (see Table 11). The pin PROP_RST of the peripheral interface is switched active LOW during the PCI reset procedure, and for the duration of the D3-hot state. Peripheral devices on board of the add-on card should use the level of this signal PROP_RST to switch themselves in any power-save mode (e.g. disable device) and reset to default settings on the rising edge of signal PROP_RST. The length of signal PROP_RST is programmable. 7.4.3 DMA AND CONFIGURABLE FIFO
DTV/DVB Transport Streams (TS) and MPEG streams (PS and TS) into the PCI memory. Each DMA channel contains inherently the definition of two buffers in the system address space, e.g. for odd and even fields in case of interlaced video, or two alternating buffers to capture continuous audio stream. The DMA channels share in time and space one common FIFO pool of 256 Dwords (1024 bytes) total. It is freely configurable how much FIFO capacity is associated with which DMA channel. Furthermore, a preferred minimum burst length can be programmed, i.e. the amount of data to be collected before the request for the PCI-bus is issued. This means that latency behaviour per DMA channel can be tailored and optimized for a given application. In the event that the FIFO of a certain channel overflows due to latency conflict on the bus, graceful overflow recovery is applied. The mount of data that gets lost because it could not be transmitted, is monitored (counted) and the PCI-bus address pointer is incremented accordingly. Thus new data will be written to the correct memory place, after the latency conflict is resolved.
The SAA7133HL supports seven DMA channels to master-write captured active video, audio, raw VBI and Table 11 Power management table POWER STATE D0 DESCRIPTION Normal operation: all functions accessible and programmable. The default setting after reset and before driver interaction (D0 un-initialized) switches most of the circuitry of the SAA7133HL into the power-down mode, effectively such as D3-hot. First step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. Most of the circuitry of the SAA7133HL is disabled with exception of the crystal and real-time clock oscillators, so that a quick recovery from D1 to D0 is possible. Second step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. All functional circuitry of the SAA7133HL is disabled, including the crystal and clock oscillators. Lowest power consumption: no functional operation. The content of the programming registers gets lost and is set to default values when returning to D0.
D1
D2
D3-hot
Table 12 FIFO configuration: typical example DMA 1 2 3 4 DATA STREAM Y U V audio DATA RATE 13.5 Mbytes/s 6.75 Mbytes/s 6.75 Mbytes/s 160 kbytes/s FIFO SIZE PROGRAMMABLE TO 384 bytes 256 bytes 256 bytes 128 bytes TOLERANT TO LATENCY OF 28.4 s 37.9 s 37.9 s 800 s
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Product specification
PCI audio and video broadcast decoder
Table 13 FIFO configuration: fastidious example DMA 1 DATA STREAM raw VBI active video, unscaled YUV 4 : 2 : 2 2 3 4 7.4.4 - MPEG stream audio - 9.5 Mbit/s 192 kbytes/s - 256 bytes 128 bytes DATA RATE 27 Mbytes/s FIFO SIZE PROGRAMMABLE TO 640 bytes
SAA7133HL
TOLERANT TO LATENCY OF 22.5 s
- 202.1 s 583.3 s
VIRTUAL AND PHYSICAL ADDRESSING
Most operating systems allocate memory to requesting applications for DMA as continuous ranges in virtual address space. The data flow over the PCI-bus points to physical addresses, usually not continuous and split in pages of 4 kbytes (Intel architecture, most UNIX systems, Power PC).
The association between the virtual (logic) address space and the fragmented physical address space is defined in page tables (system files); see Fig.10. The SAA7133HL incorporates hardware support (MMU) to translate virtual to physical addresses on the fly, by investigating the related page table information. This hardware support reduces the demand for real-time software interaction and interrupt requests, and therefore saves system resources.
physical memory handbook, full pagewidth 00000H
real-time streams
FIFO POOL 00007H DMA DEFINITIONS (VIRTUAL ADDRESS SPACE) page table 000H 0000FH
00001000H 00008000H 00009000H 0000A000H 0000D000H 00011000H 00014000H 00016000H 0001E000H
DMA ADDRESS GENERATION
007H 00017H
VIRTUAL TO PHYSICAL ADDRESS TRANSLATION
015H 0001FH
PCI TRANSFER AND CONTROL
= allocated memory space = page table
physical address space on PCI
MHB996
Fig.10 MMU implementation (shown bit width indication is valid for 4 kbytes mode).
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Product specification
PCI audio and video broadcast decoder
7.4.5 STATUS AND INTERRUPTS ON PCI-BUS
SAA7133HL
The SAA7133HL provides a set of status information about internal signal processing, video and audio standard detection, peripheral inputs and outputs (pins GPIO) and behaviour on the PCI-bus. This status information can be conditionally enabled to raise an interrupt on the PCI-bus, e.g. completion of a certain DMA channel or buffer, or change in a detected TV standard, or the state of peripheral devices. The cause of an issued interrupt is reported in a dedicated register, even if the original condition has changed before the system was able to investigate the interrupt. 7.5 Analog TV standards
TV signals that are broadcasted usually conform fairly accurately to the standards. Transmission over the air or through a cable can distort the signal with noise, echoes, crosstalk or other disturbances. Video signals from local consumer equipment, e.g. VCR, camcorder, camera, game console, or even DVD player, often do not follow the standard specification very accurately. Playback from video tape cannot be expected to maintain correct timing, especially not during feature mode (fast forward, etc.). Tables 14, 15 and 16 list some characteristics of the various TV standards. The SAA7133HL decodes all colour TV standards and non-standard signals as generated by video tape recorders e.g. automatic video standard detection can be applied, with preference options for certain standards, or the decoder can be forced to a dedicated standard. The SAA7133HL incorporates BTSC and EIAJ stereo decoding and TV mono sound decoding on chip. Baseband stereo audio can be fed into the device as analog signal.
Analog TV signals are described in three categories of standards: * Basic TV systems: defining frame rate, number of lines per field, levels of synchronization signals, blanking, black and white, signal bandwidth and the RF modulation scheme * Colour transmission: defining colour coding and modulation method * Sound and stereo: defining coding for transmission. Table 14 Overview of basic TV standards MAIN PARAMETERS RF channel width Video bandwidth 1st sound carrier Field rate Lines per frame Line frequency ITU clocks per line Sync, set-up level Gamma correction Associated colour TV standards Associated stereo TV sound systems Country examples
STANDARD UNIT M 6 4.2 4.5, FM 59.94006 525 15.734 1716 -40, 7.5 2.2 NTSC, PAL BTSC, EIAJ, A2 USA, Japan, Brazil N 6 4.2 4.5, FM 50 625 15.625 1728 -40, 7.5 2.2 PAL BTSC Argentina B 7 5 5.5, FM 50 625 15.625 1728 -43, 0 2.8 PAL dual FM, A2 part of Europe, Australia G, H 7 5 5.5, FM 50 625 15.625 1728 -43, 0 2.8 PAL NICAM Spain, Malaysia, Singapore I 8 5.5 6.0, FM 50 625 15.625 1728 -43, 0 2.8 PAL NICAM UK, Northern Europe D/K 7 6 6.5, FM 50 625 15.625 1728 -43, 0 2.8 SECAM, PAL NICAM, A2 China, Eastern Europe L 8 6 6.5, AM 50 625 15.625 1728 -43, 0 2.8 SECAM NICAM France, Eastern Europe MHz MHz MHz Hz - kHz - IRE - - - -
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 15 TV system colour standards MAIN PARAMETERS Field rate Lines per frame Chrominance subcarrier fsc to H ratio fsc offset (PAL) Alternating phase Country examples NTSC M 59.94 525 3.580 227.5 - no USA, Japan, Asia-Pacific PAL M 59.94 525 3.576 227.25 - yes Brazil PAL N 50 625 3.582 229.25 50 yes Middle and South America PAL BGHID 50 625 4.434 283.75 50 yes Europe, Commonwealth, China 4.406 282 - - SECAM LDGHK 50 625 4.250 272 - -
SAA7133HL
PAL 4.4 (60 Hz) 60 525 4.434 n.a. n.a. yes VCR transcoding NTSC-tape to PAL
UNIT Hz - MHz - Hz - -
France, Eastern Europe, Africa, Middle East
Table 16 TV stereo sound standards MAIN PARAMETERS Stereo coding scheme 2nd language De-emphasis ANALOG SYSTEMS MONO - - 75 BTSC AM mono SAP on internal FM 75, dbx-TV Noise Reduction system 15 USA, South America EIAJ FM as alternative to stereo 50 A2 (DUAL FM) 2nd FM carrier as alternative to stereo 50 or 75 DIGITAL CODING UNIT NICAM - - s DQPSK on FM mono on 1st carrier 50 or J17 internal carrier (mpx) 2-Carrier Systems (2CS)
Audio bandwidth Country examples
15 worldwide
15 Japan
15 part of Europe, Korea
15 part of Europe, China
kHz -
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.6 7.6.1 Video processing ANALOG VIDEO INPUTS
SAA7133HL
The SAA7133HL provides five analog video input pins: * Composite video signals (CVBS), from tuner or external source * S-video signals (pairs of Y-C), e.g. from camcorder * DTV/DVB `low-IF' signal, from an appropriate DTV or combi-tuner. Analog anti-alias filters are integrated on chip and therefore, no external filters are required. The device also contains automatic clamp and gain control for the video input signals, to ensure optimum utilization of the ADC conversion range. The nominal video signal amplitude is 1 V (p-p) and the gain control can adapt deviating signal levels in the range of +3 dB to -6 dB. The video inputs are digitized by two ADCs of 9-bit resolution, with a sampling rate of nominal 27 MHz (the line-locked clock) for analog video signals. 7.6.2 VIDEO SYNCHRONIZATION AND LINE-LOCKED CLOCK
The video decoder of the SAA7133HL incorporates an automatic standard detection, that does not only distinguish between 50 and 60 Hz systems, but also determines the colour standard of the video input signal. Various preferences (`look first') for automatic standard detection can be chosen, or a selected standard can be forced directly. 7.6.4 ADAPTIVE COMB FILTER
The SAA7133HL applies adaptive comb filter techniques to improve the separation of luminance and chrominance components in comparison to the separation by a chroma notch filter, as used in traditional TV colour decoder technology. The comb filter compares the signals of neighbouring lines, taking into account the phase shift of the chroma subcarrier from line to line. For NTSC the signals of three adjacent lines are investigated, and in the event of PAL the comb filter taps are spread over four lines. Comb filtering achieves higher luminance bandwidth, resulting in sharper picture and detailed resolution. Comb filtering further minimizes colour crosstalk artifacts, which would otherwise produce erroneous colours on detailed luminance structures. The comb filter as implemented in the SAA7133HL is adaptive in two ways: * Adaptive to transitions in the picture content * Adaptive to non-standard signals (e.g. VCR). The integrated digital delay lines are always exactly correct, due to the applied unique line-locked sampling scheme (LLC). Therefore the comb filter does not need to be switched off for non-standard signals and remains operating continuously. 7.6.5 MACROVISION DETECTION
The SAA7133HL recovers horizontal and vertical synchronization signals from the selected video input signal, even under extremely adverse conditions and signal distortions. Such distortions are `noise', static or dynamic echoes from broadcast over air, crosstalk from neighbouring channels or power lines (hum), cable reflections, time base errors from video tape play-back and non-standard signal levels from consumer type video equipment (e.g. cameras, DVD). The heart of this TV synchronization system is the generation of the Line-Locked Clock (LLC) of nominal 27 MHz, as defined by ITU-R BT.601. The LLC ensures orthogonal sampling, and always provides a regular pattern of synchronization signals, that is a fixed and well defined number of clock pulses per line. This is important for further video processing devices connected to the peripheral video port (pins GPIO). It is very effective to run under the LLC of 27 MHz, especially for on-board hardware MPEG encoding devices, since MPEG is defined on this clock and sampling frequency. 7.6.3 VIDEO DECODING AND AUTOMATIC STANDARD
DETECTION
The SAA7133HL incorporates colour decoding for any analog TV signal. All colour TV standards and flavours of NTSC, PAL, SECAM and non-standard signals (VCR) are automatically recognized and decoded into luminance and chrominance components, i.e. Y-CB-CR, also known as YUV. 2003 Feb 04 26
The SAA7133HL detects if the decoded video signal is copy protected by the Macrovision system. The detection logic distinguishes the three levels of the copy protection as defined in rev. 7.01, and are reported as status information. The Macrovision detection works also for copy protected video signals, which contain inverted bursts but no AGC pulses and no pseudo syncs. Those signals come from some so-called Macrovision-killer boxes. The decoded video stream is not effected directly, but application software and Operation System (OS) has to ensure, that this video stream maintains tagged as `copy protected', and such video signal would leave the system only with the reinforced copy protection. The multi-level Macrovision detection on the video capture side supports
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
proper TV re-encoding on the output point, e.g. by Philips TV encoders SAA712x or SAA7102. 7.6.6 VIDEO SCALING
SAA7133HL
240 lines of an NTSC field to 288 lines to comply with CCITT video phone formats. The scaling acquisition definition also includes cropping, frame rate reduction, and defines the amount of pixels and lines to be transported through DMA over the PCI-bus. Two programming pages are available to enable re-programming of the scaler in the `shadow' of the running processing, without holding or disturbing the flow of the video stream. Alternatively, the two programming pages can be applied to support two video destinations or applications with different scaler settings, e.g. firstly to capture video to CPU for compression (storage, video phone), and secondly to preview the picture on the monitor screen. A separate scaling region is dedicated to capture raw VBI samples, with a specific sampling rate, and be written into its own DMA channel.
The SAA7133HL incorporates a filter and processing unit to downscale or upscale the video picture in the horizontal and vertical dimension, and in frame rate (see Figs 11 and 12). The phase accuracy of the re-sampling process is 164 of the original sample distance. This is equivalent to a clock jitter of less than 1 ns. The filter depth of the anti-alias filter adapts to the scaling ratio, from 10 taps horizontally for scaling ratios close to 1 : 1, to up to 74 taps for an icon sized video picture. Most video capture applications will typically require for downscaling. But some zooming is required for conversion of ITU sampling to square pixel (SQP), or to convert the
handbook, full pagewidth
VBI first sample 1st field (odd, FID = 0) VBI region, raw samples
sample rate
VBI last sample VBI DMA 1st buffer (A) 2nd buffer (A)
VBI first line VBI last line
video region - cropped - scaled
scaling
active video area 2nd field (even, FID = 1) VBI region, raw samples video first line video region - cropped - scaled
scaling
sample rate
video DMA (A) e.g. interlaced 1st buffer (upper field) 2nd buffer (lower field)
video last line active video area
MHB997
video first pixel
video last pixel
The capture acquisition for scaling and DMA has separate programming parameters for VBI and video region and associated DMA channels.
Fig.11 Scaler processing with DMA interfacing.
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Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth
1st field (odd, FID = 0) VBI region, raw samples
sample rate
VBI DMA
1st buffer (A) video region (A) - cropped 2nd buffer (A)
scaling
3rd buffer (B) 4th buffer (B)
task "A"
active video area 2nd field (even, FID = 1) VBI region, raw samples
sample rate
video region (A) - cropped
video DMA (A) e.g. interlaced 1st buffer (upper field)
scaling
2nd buffer (lower field)
active video area 3rd field (odd, FID = 0) VBI region, raw samples
sample rate
video region (B) - skipped for field rate reduction
video DMA (B) e.g. single FID task "B" active video area 4th field (even, FID = 1) VBI region, raw samples
sample rate
1st buffer
2nd buffer (next frame)
video region - scaled down CIF
MHB998
scaling
active video area
alternating processing task A/B
Two video capture tasks can be processed in an alternating manner, without need to reprogram any scaling parameters or DMA definition.
Fig.12 Example of scaler task processing with DMA interfacing.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.6.7 VBI DATA
SAA7133HL
The Vertical Blanking Interval (VBI) is often utilized to transport data over analog video broadcast. Such data can closely relate to the actual video stream, or just be general data (e.g. news). Some examples for VBI data types are: * Closed Caption (CC) for the hearing impaired (CC, on line 21 of first field) * Intercast data [in US coded in North-American Broadcast Text System (NABTS) format, in Europe in World Standard Teletext (WST)], to transmit internet related services, optionally associated with actual video program content * Teletext, transporting news services and broadcast related information, Electronic Program Guide (EPG), widely used in Europe (coded in WST format) * EPG, broadcaster specific program and schedule information, sometimes with proprietary coding scheme (pay service), usually carried on NABTS, WST, Video Programming Service (VPS), or proprietary data coding format * Video Time Codes (VTC) as inserted in camcorders e.g. use for video editing * Copy Guard Management System (CGMS) codes, to indicate copy protected video material, sometimes combined with format information [Wide Screen Signalling (WSS)]. This information is coded in the unused lines of the vertical blanking interval, between the vertical sync pulse and the active visible video picture. So-called full-field data transmission is also possible, utilizing all video lines for data coding. The SAA7133HL supports capture of VBI data by the definition of a VBI region to be captured as raw VBI samples, that will be sliced and decoded by software on the host CPU. The raw sample stream is taken directly from the ADC and is not processed or filtered by the video decoder. The sampling rate of raw VBI can be adjusted to the needs of the data slicing software. 7.6.8 SIGNAL LEVELS AND COLOUR SPACE
along the line (corresponding to a sampling rate of 27 MHz divided by two), and a certain relationship from level to number range (see Fig.13). The video components do not use the entire number range, but leave some margin for overshoots and intermediate values during processing. For the raw VBI samples there is no official specification how to code, but it is common practice to reserve the lower quarter of the number range for the sync, and to leave some room for overmodulation beyond the nominal white amplitude (see Fig.14). The automatic clamp and gain control at the video input, together with the automatic chroma gain control of the SAA7133HL, ensures that the video components stream at the output comply to the standard levels. Beyond that additional brightness, contrast, saturation and hue control can be applied to satisfy special needs of a given application. The raw VBI samples can be adjusted independent of the active video. The SAA7133HL incorporates the YUV-to-RGB matrix (optional), the RGB-to-YUV matrix and a three channel look-up table in between (see Fig.15). Under nominal settings, the RGB space will use the same number range as defined by the ITU and shown in Fig.13a for luminance, between 16 and 235. As graphic related applications are based on full-scale RGB, i.e. 0 to 255, the range can be stretched by applying appropriate brightness, contrast and saturation values. The look-up table supports gamma correction (freely definable), and allows other non-linear signal transformation such as black stretching. The analog TV signal applies a quite strong gamma pre-compensation (2.2 for NTSC and 2.8 for PAL). As computer monitors exhibit a gamma (around 2.5), the difference between gamma pre-compensation and actual screen gamma has to be corrected, to achieve best contrast and colour impression. The SAA7133HL offers a multitude of formats to write video streams over the PCI-bus: YUV and RGB colour space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and planar formats. For legacy requirements (VfW) a clipping procedure is implemented, that allows the definition of 8 overlay rectangles. This process can alternatively be used to associate `alpha' values to the video pixels.
Analog TV video signals are decoded into its components luminance and colour difference signals (YUV) or in its digital form Y-CB-CR. ITU-R BT.601 defines 720 pixels
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
+255 +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128 U-COMPONENT
colourless
+128 V-COMPONENT
colourless
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MGC634
a. Y output range.
b. U output range (CB).
c. V output range (CR).
Fig.13 Nominal digital levels for YUV (Y, CB and CR) in accordance with ITU-R BT.601.
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
+71 +60 SYNC 1
black black shoulder
+60 SYNC
black shoulder = black
sync bottom
1
sync bottom
MGD700
a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).
b. Sources not containing black level offset.
Fig.14 Nominal digital levels for CVBS and raw VBI samples.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth
three channel non-linear transformation
Y YUV to RGB matrix
R
R RGB to YUV matrix
Y
U
G
G
U
V
B
B
V
MHB999
Fig.15 Colour space conversion and look-up table.
7.6.9
VIDEO PORT, ITU AND VIP CODES
The decoded and/or scaled video stream can be captured via PCI-DMA to the system memory, and/or can be made available locally through the video side port (VP), using some of the GPIO pins. Two types of applications are intended: * Streaming real-time video to a video side port at the VGA card, e.g. via ribbon cable over the top * Feeding video stream to a local MPEG compression device on the same PCI board, e.g. for a time shift viewing application. The video port of the SAA7133HL supports the following 8 and 16-bit wide YUV video signalling standards (see Table 6): * VMI: 8-bit wide data stream, clocked by LLC = 27 MHz, with discrete sync signals HSYNC, VSYNC and VACTIVE * ITU-R BT.656, parallel: 8-bit wide data stream, clocked by LLC = 27 MHz, synchronization coded in SAV and EAV codes * VIP 1.1 and 2.0: 8-bit or 16-bit wide data stream, clocked by LLC = 27 MHz, synchronization coded in SAV and EAV codes (with VIP extensions) * Zoom Video (ZV): 16-bit wide pixel stream, clocked by LLC/2 = 13.5 MHz, with discrete sync signals HSYNC and VSYNC * ITU-R BT.601 direct (DMSD): 16-bit wide pixel stream, clocked by LLC = 27 MHz, with discrete sync signals HSYNC, VSYNC/FID and CREF
* Raw DTV/DVB sample stream: 9-bit wide data, clocked with a copy of signal X_CLK_IN. The VIP standard is designed to transport scaled video and discontinuous data stream by allowing the insertion of `00' as marker for empty clock cycles. For the other video port standards, a data valid flag or gated clock can be applied. 7.7 7.7.1 TV sound TV SOUND STEREO DECODING
The SAA7133 HL incorporates TV sound decoding from the Sound Intermediate Frequency (SIF) signal. The analog SIF signal is taken from the tuner, digitized and digitally FM or AM demodulated. If one of the supported TV sound standards is found (BTSC, EIAJ, mono), the pilot tone is investigated (mono, stereo, dual) and the signal is properly stereo or dual decoded. The SAA7133HL supports the stereo audio standards BTSC (+SAP) and EIAJ and all mono standards on-chip. dbx-TV Noise Reduction and de-emphasis filters are also integrated. The digital FM demodulation maintains stable phase accuracy, resulting into improved channel separation, compared to traditional analog demodulation. TV sound decoding operates at a 32 kHz sample rate, resulting in an audio bandwidth of up to 15 kHz. The SAA7133HL incorporates baseband stereo audio ADCs, to capture sound signals associated with external video sources, e.g. camera, camcorder or VCR.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
For concurrent capture of audio and video signals, it is important to maintain synchronization between the two streams. The spoken word and other sound should match the displayed picture within a video frame (1/30 s respectively 1/25 s `lip-sync'). The SAA7133HL has special means to lock the audio sampling clock to the video frame
SAA7133HL
frequency (FLC), so that a programmable but constant number of audio samples is associated with each video frame. This is especially important for video editing, compression and recording, e.g. time shift viewing. There is no drift between the audio and video streams, not even for longer recording times.
Table 17 TV sound decoding, supported feature processing and sampling rate INPUT AND SOUND STANDARD SUPPORTED FUNCTION BTSC Decoding Analog audio output to loop back cable I2S output Signal Sample rate PCI (audio streaming) Signal Sample rate Feature processing Volume and balance Bass and treble Incredible Stereo Incredible Mono Notes 1. Simultaneous decoding of stereo and SAP. dbx-TV Noise Reduction either on stereo or on SAP. 2. Default pass-through of L1 and R1. 7.7.2 ADDITIONAL AUDIO FEATURES X X X if SAP X X X either of dual X X X - X X - X X X - X X X X - mono or stereo mono or and/or SAP stereo or dual 32 kHz mono or stereo 32 or 48 kHz mono mono or 2 x mono stereo mono or stereo mono or or SAP stereo or dual mono or stereo mono mono or 2 x mono stereo SIF FROM TUNER EIAJ FM RADIO OTHER AM/FM mono or stereo mono or stereo mono mono BASEBAND AUDIO L OR R mono or 2 x mono mono or 2 x mono L AND R stereo stereo(2)
mono or mono or stereo stereo or dual and SAP(1) mono or stereo mono or or SAP stereo or dual
32 kHz
32, 44.1 or 48 kHz
32, 44.1 or 48 kHz
The SAA7133HL provides several audio control and enhancement features, like * Bass, treble, balance and volume control * Automatic volume levelling (this algorithm lowers louder parts, e.g. commercials) * Incredible Mono (this algorithm adds stereo-like sound impression to monaural audio signals) * Incredible Stereo (this algorithm makes stereo sound impression `wider'. The distance between the two loudspeakers seems to become larger) * FM radio stereo decoding.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.7.3 AUDIO INTERFACES
SAA7133HL
The SIF input can handle the sound subcarrier signal from the tuner. Baseband audio signals can be captured through the stereo line-in inputs LEFT1, RIGHT1, LEFT2 and RIGHT2 or the I2S-bus input. The decoded and possibly enhanced digital audio stream can be captured through dedicated DMA into the PCI memory space, or to the output in I2S-bus format, e.g. to a peripheral digital sound amplifier. The third way is to re-convert the audio signal to analog via the integrated audio stereo DACs and feed it directly through the loop back cable to the sound card or to headphones for local monitoring. A master clock output (A_CLK_master) for synchronous clocking of external devices is available via a GPIO output. The audio block is also able to work synchronously to an external audio reference clock (A_REF_CLK). 7.7.4 DEFAULT ANALOG AUDIO PASS-THROUGH AND LOOP
BACK CABLE
The SAA7133HL supports also capturing of MPEG elementary and program streams. This expands the connectivity to MPEG encoders like the Philips SAA6752HS or similar devices. 7.9 7.9.1 Control of peripheral devices I2C-BUS MASTER
The SAA7133HL incorporates an I2C-bus master to set-up and control peripheral devices such as tuner, DTV/DVB channel decoder, audio DSP co-processors, etc. The I2C-bus interface itself is controlled from the PCI-bus on a command level, reading and writing byte by byte. The actual I2C-bus status is reported (status register) and, as an option, can raise error interrupts on the PCI-bus. At PCI reset time, the I2C-bus master receives board specific information from the on-board EEPROM to update the PCI configuration registers. The I2C-bus interface is multi-master capable and can assume slave operation too. This allows application of the device in the stand-alone mode, i.e. with the PCI-bus not connected. Under the slave mode, all internal programming registers can be reached via the I2C-bus with exception of the PCI configuration space. 7.9.2 PROPAGATE RESET
Most operating systems are prepared to deal with audio input at only one single entry point, namely at the sound card function. Therefore the sound associated with video has to get routed through the sound card. The SAA7133HL supports analog audio pass-through and the loop back cable on-chip. No external components are required. The audio signal, that was otherwise connected to the sound card line-in, e.g. analog sound from a CD-ROM drive, has to be connected to one of the inputs of the SAA7133HL. By default, after a system reset and without involvement of any driver, this audio signal is passed through to the analog audio output pins, that will feed the loop back cable to the sound card line-in connector. The AV capture driver has to open the default pass-through and switch in the TV sound signal by will. 7.8 DTV/DVB channel decoding and MPEG TS or PS capture
The PCI system reset and ACPI power management state D3 is propagated to peripheral devices by the dedicated pin PROP_RST. This signal is switched to active LOW by reset and D3, and is only switched HIGH under control of the device driver `by will'. The intention is that peripheral devices will use signal PROP_RST as Chip-Enable (CE). The peripheral devices should enter a low power consumption state if pin PROP_RST = LOW, and reset into default setting at the rising edge. 7.9.3 GPIO
The SAA7133HL also supports application extension to cover the reception of digital TV broadcast [DTV/ATSC, DVB (T/C/S) or BS-digital]. The low IF signal from a hybrid tuner is fed to a peripheral channel decoder, to decode it into the transport stream. This TS, accompanied by a clock and handshake signals [Start Of Packet (SOP), etc.] can be captured by the SAA7133HL, in serial or parallel format. The TS packets are written in a structured way in dedicated DMA definition into the PCI memory space. Toggling between two DMA buffers is supported automatically.
The SAA7133HL offers a set of General Purpose Input/Output (GPIO) pins, to interface to on-board peripheral circuits; see also Table 6. These GPIOs are intended to take over dedicated functions: * Digital video port output: 8-bit or 16-bit wide (including raw DTV) * Digital audio serial output: i.e. I2S-bus output * Transport stream input: - parallel (also applicable for program stream and elementary stream) - serial (also applicable as I2S-bus input)
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
* Peripheral interrupt input: four GPIO pins of the SAA7133HL can be enabled to raise an interrupt on the PCI-bus. By this means, peripheral devices can directly intercept with the device driver on changed status or error conditions. Any GPIO pin that is not used for a dedicated function is available for direct read and write access via the PCI-bus. Any GPIO pin can be selected individually as input or output (masked write). By these means, very tailored interfacing to peripheral devices can be created via the SAA7133HL capture driver running on Windows operating systems. At system reset (PCI reset) all GPIO pins will be set to 3-state and input, and the logic level present on the GPIO pins at that moment will be saved into a special `strap' register. All GPIO pins have an internal pull-down resistor (LOW level), but can be strapped externally with a 4.7 k resistor to the supply voltage (HIGH level). The device driver can investigate the strap register for information about the hardware configuration of a given board. 8 BOUNDARY SCAN TEST
SAA7133HL
BST-test can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7133HL is available on request. 8.1 Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state if pin TRST is at LOW level. 8.2 Device identification codes
The SAA7133HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7133HL follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 18). Details about the JTAG Table 18 BST instructions supported by the SAA7133HL INSTRUCTION BYPASS EXTEST SAMPLE
When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected internally between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level, this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO) (see Fig.16). A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.
DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. 34
CLAMP IDCODE
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth
MSB 31 TDI 28 27 0111000100110011 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1
LSB 0 1 TDO
0001
4-bit version code
mandatory
MBL706
Fig.16 32 bits of identification code.
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together. SYMBOL VDDD VDDA VSS VIA VI(n) VID PARAMETER digital supply voltage analog supply voltage voltage difference between pins VSSA and VSSD input voltage at analog inputs input voltage at pins XTALI, SDA and SCL input voltage at digital I/O stages outputs in 3-state; -0.5 V < VDDD < 3.0 V outputs in 3-state; 3.0 V < VDDD < 3.6 V Tstg Tamb Vesd storage temperature ambient temperature electrostatic discharge voltage note 1 note 2 Notes 1. Machine model: L = 0.75 H, C = 200 pF and R = 0 . 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note 1. The overall Rth(j-a) value can differ between 35 K/W and 30 K/W depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area direct under the SAA7133HL with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. PARAMETER CONDITIONS VALUE 30.7(1) UNIT K/W CONDITIONS MIN. -0.5 -0.5 - -0.5 -0.5 -0.5 -0.5 -65 0 -250 MAX. +4.6 +4.6 100 +4.6 +4.6 +5.5 +150 70 +200 UNIT V V mV V V V C C V V
VDDD + 0.5 V
-3500 +3500
thermal resistance from junction to ambient in free air
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
11 CHARACTERISTICS For minimum and maximum values: VDDD = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; Tamb = 0 to 70 C; for typical values: VDDD = 3.3 V; VDDA = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD VDDA P digital supply voltage analog supply voltage power dissipation power state D0 for typical application - D0 after reset D1 D2 D3-hot Crystal oscillator fxtal(nom) fxtal(n) fxtal Pdrive tj VIH(XTALI) VIL(XTALI) nominal crystal frequency permissible nominal frequency deviation oscillator frequency range crystal power level of drive at pin XTALO oscillator clock jitter HIGH-level input voltage at pin XTALI LOW-level input voltage at pin XTALI crystal 1; see Table 19 crystal 2; see Table 19 - - - 24 - - 2 -0.3 32.11 - 32.11 0.5 - - - - - - - - 1.35 0.15 0.2 0.15 - 3.0 3.0 3.3 3.3 PARAMETER CONDITIONS MIN. TYP.
SAA7133HL
MAX.
UNIT
3.6 3.6 1.6 - - - 0.02
V V W W W W W
MHz MHz 10-6 MHz mW ps V V
24.576 - 70 x 33 - 100 VDDD + 0.3 +0.8
PCI-bus inputs and outputs VIH VIL ILIH ILIL VOH VOL Ci HIGH-level input voltage LOW-level input voltage HIGH-level input leakage current LOW-level input leakage current HIGH-level output voltage LOW-level output voltage input capacitance at pin PCI_CLK pin IDSEL other input pins SRr SRf output rise slew rate output fall slew rate 0.4 to 2.4 V; note 3 2.4 to 0.4 V; note 3 5 - - 1 1 - - - - - 12 8 10 5 5 pF pF pF V/ns V/ns VI = 2.7 V; note 1 VI = 0.5 V; note 1 IO = -2 mA IO = 3 or 6 mA; note 2 2 -0.5 - - 2.4 - - - - - - - 5.75 +0.8 10 -10 - 0.55 V V A A V V
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL tval
PARAMETER CLK to signal valid delay
CONDITIONS see Fig.17; note 4 bused signals point-to-point signals 2 2 2 - 7
MIN.
TYP. - - - - - - - - - 11 12 - 28 - - - - 40
MAX.
UNIT ns ns ns ns ns ns ns s ns
ton toff tsu
float-to-active delay active-to-float delay input set-up time to CLK
see Fig.17; note 5 see Fig.17; note 5 see Fig.17; note 4 bused signals point-to-point signals
10 (12) 0 100 -
th trst(CLK) trst(off)
input hold time from CLK reset active time after CLK stable reset active to output float delay
see Fig.17 note 6 notes 5, 6 and 7
I2C-bus interface, compatible to 3.3 and 5 V signalling (pins SDA and SCL) fbit VIL VIH VOL bit frequency rate LOW-level input voltage HIGH-level input voltage LOW-level output voltage note 8 note 8 Io(sink) = 3 mA 0 -0.5 - - - - 400 0.3VDD(I2C) 0.4 kbits/s V V
0.7VDD(I2C) -
VDD(I2C) + 0.5 V
Analog video inputs INPUTS (PINS CV0 TO CV4) Iclamp Vi(p-p) Ci cs B dif Gdif LEDC(d) LEDC(i) S/N ENOB clamping current input voltage (peak-to-peak value) input capacitance DC input voltage VI = 0.9 V - note 9 0.375 - fi < 5 MHz at -3 dB; ADC only; note 10 amplifier plus anti-alias filter bypassed amplifier plus anti-alias filter bypassed - - - - - - fi = 4 MHz; anti-alias filter bypassed; AGC = 0 dB fi = 4 MHz; anti-alias filter bypassed; AGC = 0 dB - - 8 0.75 - - 7 2 2 1.4 2 50 8 - 1.07 10 -50 - - - - - - - A V pF
9-BIT ANALOG-TO-DIGITAL CONVERTERS channel crosstalk analog bandwidth differential phase differential gain DC differential linearity error DC integral linearity error signal-to-noise ratio effective number of bits dB MHz deg % LSB LSB dB bit
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL
PARAMETER
CONDITIONS - - - -
MIN.
TYP. - - - - - 12 - 11
MAX.
UNIT
Analog sound input (pin SIF) Vi(max)(p-p) maximum input voltage (peak-to-peak value) input level adjustment at 0 dB input level adjustment at -10 dB Vi(min)(p-p) minimum input voltage for lower limit of AGC (peak-to-peak value) AGC range of sound input input frequency input resistance input capacitance default pre-gain selection for pin SIF (0 dB) input level adjustment at 0 dB input level adjustment at -10 dB 941 2976 59 188 24 - - 7.5 mV mV mV mV dB MHz k pF
AGC fi Ri Ci
in addition to 0 and -10 dB - switch 3 10 -
Analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) and outputs (pins OUT_LEFT and OUT_RIGHT) Vi(nom)(rms) Vi(max)(rms) Vo(nom)(rms) Vo(max)(rms) Ri Ro RL(AC) CL Voffset(DC) THD + N nominal input voltage (RMS value) maximum input voltage (RMS value) nominal output voltage (RMS value) maximum output voltage (RMS value) input resistance output resistance AC load resistance output load capacitance static DC offset voltage total harmonic distortion-plus-noise signal-to-noise ratio Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth B = 20 Hz to 20 kHz note 11 THD < 3%; note 12 note 11 THD < 3% Vi(max) = 1 V (RMS) Vi(max) = 2 V (RMS) - - - - - - 150 10 - - - 200 1 180 1 145 48 250 - - 10 0.1 - 2 - - - - 375 - 12 30 0.3 mV V mV V k k k nF mV %
S/N
reference voltage 70 Vo = 1 V (RMS); fi = 1 kHz; "ITU-R BS.468" weighted; quasi peak between any analog input pairs; fi = 1 kHz between left and right of each input pair 60 60
75
-
dB
ct cs
crosstalk attenuation channel separation
- -
- -
dB dB
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Sound demodulator performance; note 13 AUDIO AM MONO CHARACTERISTICS (DDEP STANDARD CODE = 10) S/NAM AM demodulator signal-to-noise ratio AM carrier 6.5 MHz; 54% AM; fi = 1 kHz; second SIF AGC off; "ITU-R BS.468" weighted; quasi peak AM carrier 6.5 MHz; 54% AM; fi = 1 kHz; second SIF AGC off; "ITU-R BS.468" weighted; quasi peak reference f = 1 kHz; no clipping - 47 - dB
THD + NAM
total harmonic distortion-plus-noise of AM demodulator
-
0.43
-
%
Gresp(AM)
AM frequency response from 20 Hz to 15 kHz
-
-0.5 to - +0.1 -
dB
AUDIO M STANDARD BTSC CHARACTERISTICS (DDEP STANDARD CODE = 13) S/NBTSC BTSC decoder output signal-to-noise ratio BTSC stereo with L or R only; 100% modulation; fi = 1 kHz; unweighted RMS BTSC stereo with L or R only; 100% modulation; fi = 1 kHz; unweighted RMS 100% modulation; fi = 1 kHz; compromise de-emphasis (SAPDBX = 0); bandwidth B = 0 to 15 kHz; unweighted RMS 100% modulation; fi = 1 kHz; compromise de-emphasis (SAPDBX = 0); bandwidth B = 0 to 15 kHz; unweighted RMS 1 kHz L or R or SAP; 100% modulation; spectral at 1 kHz BTSC to SAP SAP to BTSC cs(stereo) BTSC stereo channel separation L or R only; 50 Hz to 10 kHz 10% EIM 1 to 66% EIM - - 32 27 - - dB dB - - >80 >80 - - dB dB - 77 dB
THD + NBTSC total harmonic distortion-plus-noise of BTSC decoder output S/NSAP SAP decoder output signal-to-noise ratio
-
0.23
-
%
-
59
-
dB
THD + NSAP
total harmonic distortion-plus-noise of SAP decoder output
-
0.27
-
%
ct
crosstalk attenuation
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL Gresp(BTSC)
PARAMETER BTSC frequency response
CONDITIONS 30% modulation; reference f = 1 kHz stereo; L or R only mono; L = R - -
MIN.
TYP.
MAX.
UNIT
-0.4 to - +1.5 -0.2 to - +0.04 -
dB dB
AUDIO M STANDARD EIAJ CHARACTERISTICS (DDEP STANDARD CODE = 14) S/NEIAJ EIAJ decoder output signal-to-noise ratio EIAJ stereo with L or R; 100% modulation; fi = 1 kHz; unweighted RMS EIAJ stereo with L or R; 100% modulation; fi = 1 kHz; unweighted RMS - 61 dB
THD + NEIAJ
total harmonic distortion-plus-noise of EIAJ decoder output
-
0.17
-
%
S/NSUB
EIAJ sub-channel decoder EIAJ dual; output signal-to-noise ratio 100% modulation; fi = 1 kHz; unweighted RMS total harmonic distortion-plus-noise of EIAJ sub-channel decoder output EIAJ dual crosstalk attenuation EIAJ dual; 100% modulation; fi = 1 kHz; unweighted RMS 100% modulation; fi = 1 kHz main to sub-channel sub to main channel
-
59
-
dB
THD + NSUB
-
0.8
-
%
ct
- -
80 80
- -
dB dB
cs(stereo)
EIAJ stereo channel separation
50% modulation; selective RMS; L or R 100 Hz to 5 kHz 50 Hz to 8 kHz - - - 38 28 - - dB dB dB
Gresp(EIAJ)
EIAJ frequency response from 20 Hz to 12 kHz
EIAJ stereo; 15% modulation; reference f = 1 kHz
-0.9 to - +0.1
AUDIO FM RADIO CHARACTERISTICS (DDEP STANDARD CODE = 15 TO 18) S/Nradio FM radio decoder output signal-to-noise ratio FM radio stereo with L or R - only; 10.7 MHz carrier; 100% modulation; fi = 1 kHz; 75 s de-emphasis; unweighted RMS 55 - dB
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL THD + Nradio
PARAMETER total harmonic distortion-plus-noise of FM radio decoder output
CONDITIONS FM radio stereo with L or R - only; 10.7 MHz carrier; 100% modulation; fi = 1 kHz; 75 s de-emphasis; unweighted RMS 60% modulation; selective RMS; pre-emphasis off; 100 Hz to 14 kHz FM radio stereo; 10.7 MHz carrier; 75 s de-emphasis; 30% modulation; reference f = 1 kHz -
MIN.
TYP. 0.2 -
MAX.
UNIT %
cs(stereo)
FM radio stereo channel separation
45 to 55
-
dB
Gresp(radio)
FM radio frequency response from 20 Hz to 15 kHz
-
-0.2 to - +0.4
dB
AUDIO IDENTIFICATION OF EIAJ MONO/STEREO (JAPANESE) STANDARDS mpilot modulation degree of pilot tone nominal pilot level and identification frequency; no overmodulation European system Japanese system fident(EIAJ) identification frequency window M standard (EIAJ) stereo; slow mode M standard (EIAJ) stereo; fast mode M standard (EIAJ) dual; slow mode M standard (EIAJ) dual; fast mode tident total identification time on or off slow mode fast mode - - - 10 21 981.9 to 983.0 979.7 to 985.1 921.8 to 923.0 919.3 to 925.8 2 0.5 - - - % % Hz
-
-
Hz
-
-
Hz
-
-
Hz
- - - - - -
- - - - - -
s s
AUDIO AUTOMATIC STANDARD DETECTION (ASD) TIMING; STDSEL = 1DH tASD(mono) tASD(stereo) time to auto-detect mono sound standard time to auto-detect stereo or multi-channel sound standard default threshold settings BTSC stereo BTSC SAP EIAJ 65 0.25 0.3 0.5 ms s s s
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os: GPIO pins and BST test pins (5 V tolerant) PINS GPIO0 TO GPIO23, V_CLK, GPIO25 TO GPIO27, TDI, TDO, TMS, TCK AND TRST VIH VIL ILI IL(I/O) Ci Rpd Rpu VOH VOL HIGH-level input voltage LOW-level input voltage input leakage current I/O leakage current input capacitance pull-down resistance pull-up resistance HIGH-level output voltage LOW-level output voltage 3.3 V signal levels at VDDD 3.3 V I/O at high-impedance VI = VDDD VI = 0 IO = -2 mA IO = 2 mA 2.0 -0.3 - - - - - 2.4 0 - - - - - 50 50 - - 5.5 +0.8 1 10 8 - - VDDD + 0.5 0.4 V V A A pF k k V V
Audio-video port outputs (digital video stream from comb filter decoder or scaler, digital audio from sound decoder or baseband audio inputs via I2S-bus) LLC AND LLC2 CLOCK OUTPUT ON PIN V_CLK (see Fig.18) CL Tcy load capacitance cycle time duty factor LLC active LLC2 active CL = 40 pF; note 14 LCC active LCC2 active tr tf CL th rise time fall time 0.4 to 2.4 V 2.4 to 0.4 V 35 35 - - 15 notes 15 and 16 LLC active LLC2 active tPD propagation delay from positive edge of signal V_CLK notes 15 and 16 LLC active LLC2 active - - - - 28 55 ns ns 5 15 - - - - ns ns - - - - - 65 65 5 5 % % ns ns 15 35 70 - - - 50 39 78 pF ns ns
VIDEO DATA OUTPUT WITH RESPECT TO SIGNAL V_CLK ON PINS GPIO0 TO GPIO17, GPIO22 AND GPIO23 (see Fig.18) load capacitance data hold time 50 pF
Raw DTV/DVB outputs (reuse of video ADCs in DVB/TV applications) CLOCK INPUT SIGNAL X_CLK_IN ON PIN GPIO18 Tcy tr tf CL cycle time duty factor rise time fall time note 14 0.8 to 2.0 V 2.0 to 0.8 V 27.8 40 - - - 37 50 - - - 333 60 5 5 ns % ns ns
CLOCK OUTPUT SIGNAL ADC_CLK ON PIN V_CLK load capacitance 25 pF
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
SYMBOL Tcy tr tf CL th tPD
PARAMETER cycle time duty factor rise time fall time
CONDITIONS CL = 40 pF; note 14 0.4 to 2.4 V 2.4 to 0.4 V 40 - - 25 inverted and not delayed; note 15 inverted and not delayed; notes 15 and 17 5 -
MIN. 27.8
TYP. - - - - - - - - 60 5 5
MAX.
UNIT ns % ns ns
VSB DATA OUTPUT SIGNALS WITH RESPECT TO SIGNAL ADC_CLK load capacitance data hold time propagation delay from positive edge of signal ADC_CLK 50 - 23 pF ns ns
TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19) Tcy tr tf cycle time duty factor rise time fall time note 14 0.8 to 2.0 V 2.0 to 0.8 V - 40 - - 333 - - - - 60 5 5 ns % ns ns
DATA AND CONTROL INPUT SIGNALS ON TS-P PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO0 TO GPIO7, GPIO16, GPIO19 AND GPIO22 (see Fig.19) tsu(D) th(D) input data set-up time input data hold time 3 8 - - - - ns ns
TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19) Tcy tr tf cycle time duty factor rise time fall time note 14 0.8 to 2.0 V 2.0 to 0.8 V 37 40 - - - - - - - 60 5 5 ns % ns ns
DATA AND CONTROL INPUT SIGNALS ON TS-S PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO16, GPIO19, GPIO21 AND GPIO22 (see Fig.19) tsu(D) th(D) Notes 1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs. 2. Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA; these are pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. 4. REQ# and GNT# are point-to-point signals and have different output valid delay and input set-up times than bused signals. GNT# has a set-up time of 10 ns. REQ# has a set-up time of 12 ns. input data set-up time input data hold time 3 8 - - - - ns ns
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
5. For purposes of active or float timing measurements, the high-impedance or `off' state is defined to be when the total current delivered through the device is less than or equal to the leakage current specification. 6. RST is asserted and de-asserted asynchronously with respect to CLK. 7. All output drivers floated asynchronously when RST is active. 8. VDD(I2C) is the extended pull-up voltage of the I2C-bus (3.3 or 5 V bus). 9. Nominal analog video input signal is to be terminated by 75 that results in 1 V (p-p) amplitude. This termination resistor should be split into 18 and 56 , and the dividing tap should feed the video input pin, via a coupling capacitor of 47 nF, to achieve a control range from -3 dB (attenuation) to +6 dB (amplification) for the internal automatic gain control. See also the application note of the SAA7133HL. 10. See user manual SAA7133HL for Anti-Alias Filter (AAF). 11. Definition of levels and level setting: a) The full-scale level for analog audio signals VFS = 0.8 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (FS). b) Nominal audio input levels: external, mono, Vi = 180 mV (RMS); -15 dB (FS). 12. The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS) and 2 V (RMS), selectable independently per stereo input pair, LEFT1, RIGHT1 and LEFT2, RIGHT2. 13. VDDA = 3.3 V; Vi(SIF) = 196 mV (RMS); level and gain settings according to note 11; for external components see the application diagram in SAA7133HL application notes; unless otherwise specified. tH 14. The definition of the duty factor: = ------T cy 15. The output timing must be measured with the load of a 30 pF capacitor to ground and a 500 resistor to 1.4 V. 16. Signal V_CLK inverted; not delayed (default set-up). 17. tPD = 6 ns + 0.6TADC_CLK in ns (TADC_CLK = 28 ns).
handbook, full pagewidth
2.4 V CLK 1.5 V tval OUTPUT DELAY 1.5 V
0.4 V
3-STATE OUTPUT ton toff tsu INPUT 1.5 V input valid th 2.4 V 1.5 V 0.4 V
MGG280
Fig.17 PCI I/O timing.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth
t PD th
video data and control output (pins GPIO0 to GPIO 17, GPIO 22 and GPIO23) tH tL
2.4 V 0.4 V
2.4 V clock output (pin V_CLK) 1.5 V 0.4 V tf tr
MHC002
Fig.18 Data output timing (video data, control outputs and raw DTV/DVB).
handbook, full pagewidth and TS data
control input (pins GPIO0 to GPIO 7, GPIO 16, GPIO19 and GPIO21) t su(D) t h(D)
2.0 V 0.8 V
2.0 V TS_CLK (pin GPIO20) 1.5 V 0.8 V tr tf
MHC003
Fig.19 Data input timing (TS data and control inputs).
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 19 Specification of crystals and related applications (examples); note 1 CRYSTAL FREQUENCY 32.11 MHz STANDARD FUNDAMENTAL 1B Crystal specification Typical load capacitance Maximum series resonance resistance Typical motional capacitance Maximum parallel capacitance Maximum permissible deviation Maximum temperature deviation External components Typical load capacitance at pin XTALI Typical load capacitance at pin XTALO Typical capacitance of LC filter Typical inductance of LC filter Note 1. For oscillator application, see the application note of the SAA7133HL. 33 10 15 27 5.6 20 30 20 7 8 60 13.5 3 1 8 50 1.5 4.3 30 x 10-6 30 x 10-6 20 30 20 7 8 60 1 3.3 1C 3rd HARMONIC 1A FUNDAMENTAL 2B 2C 24.576 MHz
SAA7133HL
UNIT 3rd HARMONIC 2A
10 80 1.5 3.5 50 x 10-6 20 x 10-6
pF fF pF
30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6
30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6
18
pF
33
10
15
27
5.6
18
pF
n.a. n.a.
n.a. n.a.
1 4.7
n.a. n.a.
n.a. n.a.
1 4.7
nF H
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
12 PACKAGE OUTLINE LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SAA7133HL
SOT425-1
c
y X
A 102 103 65 64 ZE
e E HE A A2 A 1
(A 3) Lp L detail X
wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 0o
o
22.15 16.15 21.85 15.85
ISSUE DATE 99-12-27 00-01-19
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
13 SOLDERING 13.1 Introduction to soldering surface mount packages
SAA7133HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes not suitable not suitable(3)
SAA7133HL
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
14 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
SAA7133HL
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
ICs with MPEG-audio/AC-3 audio functionality Purchase of a Philips IC with an MPEG-audio and/or AC-3 audio functionality does not convey an implied license under any patent right to use this IC in any MPEG-audio or AC-3 audio application. For more information please contact the nearest Philips Semiconductors sales office or e-mail: licensing.cip@philips.com. 17 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7133HL
ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2003 Feb 04
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/01/pp52
Date of release: 2003
Feb 04
Document order number:
9397 750 10353

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